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Verilog Coding for Logic Synthesis, by Weng Fook Lee
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Provides a practical approach to Verilog design and problem solving.
* Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
* Includes over 90 design examples.
* There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
* Book is suitable for use as a textbook in EE departments that have VLSI courses
- Sales Rank: #4268850 in Books
- Brand: Brand: Wiley-Interscience
- Published on: 2003-04-17
- Original language: English
- Number of items: 1
- Dimensions: 9.41" h x .83" w x 6.42" l, 1.31 pounds
- Binding: Hardcover
- 336 pages
- Used Book in Good Condition
Most helpful customer reviews
1 of 1 people found the following review helpful.
Sparse Index
By Alan M. Feldstein
This is a 309-page book with a one and a half page index! I can't count how many times I have pulled out this book, looked for a particular topic in its index, and put the book back on the shelf.
Not obvious from the title, although Lee says so on the back cover, this book describes a design flow for ASIC design. That makes me wonder if there exists a Verilog book that describes a design flow for microprocessor design.
A reasonable introduction to Verilog is provided on the CD accompanying "Computer Organization and Design: The Hardware/Software Interface", Third Edition. [...]
For an HDL-independent explanation of register-transfer-level (RTL) and behavioral modeling, I really like Figure 1-1 in "The Designer's Guide to VHDL" and its accompanying text, although Peter Ashendon gives credit to Gajski and Kuhn ("New VLSI Tools", IEEE Computer, Vol. 16, No. 12, December 1983, pp. 11-14) for devising the figure. Lee's book, like so many others, doesn't do a good job on these concepts.
Of course, there is no substitute for IEEE Std 1364-2001 (and IEEE Std 1364.1-2002 defining the RTL subset).
2 of 3 people found the following review helpful.
Great reference for synthesizable verilog
By a.h.
This book is an excellent reference for writing synthesizable verilog. Chapter 4 (Best Known Methods for Synthesis) gives useful example and explaination on this matter. Such knowledge is usually only attainable through experience.
I find this book very useful, and would highly recommend it to students and new designers (even experienced designers too!). It will definitely help them in coding synthesizable verilog for tape-out!
2 of 3 people found the following review helpful.
No use !
By Meto
Don't buy this book! Its useless, neither for beginners nor for advanced people(anyway). I went thru this book in couple of hours, found ridiciolous simple mistakes in it, Book has "for Syntheis" in its name but found so many rubbish pages full with some stupid simulation results. Well, one can find better docs on the Net just for free, instead of buying this book.
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